Show all publications

A System-Level Fpga-Based Hardware-in-the-Loop Test of High-Speed Train

Open DOI PageDownload Bibliography in Open DocumentDownload Bibliography in HTMLDownload BibTeXDownload RISDownload Bibliographical Ontology (RDF)
Authors:
Details:
In IEEE Transactions on Transportation Electrification, vol. 4(4), pp. 912-921, 2018.
ISSN 2332-7782
DOI: 10.1109/TTE.2018.2866696.
Abstract:
Hardware-in-the-loop (HIL) test provides a timesaving and safe environment for testing high-power electronic systems. But the main difficulty for the HIL test of power electronic system lies on the modeling of the complex and highpower system. This paper proposes a modeling method of the electrical system of high-speed train. With this method, the HIL test platform using field-programmable gate array (FPGA) boards is built. Besides, in order to meet the computing power requirement of the system modeling, we simulate the whole system using two dSPACE simulators and inside each dSPACE simulator, a multi-processor system is achieved through Gigalink connection. The whole HIL system can be used to evaluate both the hardware and software performance of traction control unit (TCU) and auxiliary control unit (ACU). The HIL results under steady state and transient conditions demonstrate modeling accuracy and provide a detailed insight into its development.
Keywords:
,
Publication Category:
International journal with reading committee
Copyright 2010-2019 © Laboratoire Connaissance et Intelligence Artificielle Distribu√©es - Université Bourgogne Franche-Comté - Privacy policy